OneStopForAllVLSI

Your own Verilog lab: you write both the module and the testbench, then simulate—no hidden harness.

• Naming tip: Keep your top-level module named top (and in Sandbox keep your testbench module named tb) to avoid config issues when moving between Sandbox, Practice, and Zoi Code.
• Use the Module and Testbench tabs in the editor, then click Run (Ctrl/⌘+Enter). That submits your pair to the simulator and polls until results are ready.
• Output tab: build logs, $display output, and errors.
• Waveform tab: when your testbench dumps VCD (e.g. dump.vcd), use Basic (WaveDrom) or Interactive (Surfer) inside the tab to explore signals.
• Synthesis tab: run Yosys on your module code to see a gate-level netlist and stats (available whenever your design is non-empty).
• Dock controls move the whole output pane (Output / Waveform / Synthesis)—e.g. Dock: Bottom vs Dock: Right—so you can match your screen layout.

Curated problems from our collections. You read the statement, implement the requested module, and your code is checked against hidden tests—like a take-home, but in the browser.

• Sign in to submit. The grader runs your solution against tests you don’t see; open the Results tab for pass/fail and feedback.
• Waveform unlocks after a passing run that produced waveform data—same Basic / Interactive viewers as Sandbox.
• Notes tab: rich-text notes auto-saved with the problem.
• Synthesis is available after you’ve passed with waveform data recorded—then you can synthesize and compare netlist/stats like in Sandbox.
• Dock options match Sandbox so you can park the output strip on the side or bottom while you code.

The graded problem set path: structured Verilog challenges with visible test-case scaffolding plus full judge, output, and (when you pass) waveforms.

• Open a problem’s Test cases tab to see what’s being exercised, write your design in the editor, then submit for judging.
• Results shows simulator output and verdict; Waveform appears after a pass with VCD—Basic vs Interactive viewers apply here too.
• Notes for your own write-up, auto-saved per problem.
• Synthesis follows the same rule as Practice: enabled after a passed submission with waveform data, so your pipeline (judge → waves → synth) is complete.
• Use Dock to keep code wide while monitoring Output / Waveform / Synthesis.