Verilog Basics

Module 1 • 1h 20m

In this comprehensive module, we explore the fundamental syntax of Verilog HDL. You will learn about data types, modules, operators, and how to write efficient RTL code.

Discussion 12

Jane Doe

2 hours ago

Can someone explain the difference between blocking and non-blocking assignments again? I'm slightly confused about the race conditions.

Notes

Key Concepts

Verilog is a Hardware Description Language (HDL). It is used to model electronic systems.

Modules: Basic building blocks.
Ports: Interfaces to the outside world.

module test(input a, output b);
assign b = ~a;
endmodule

Assignment

Implement a 4-bit counter using the concepts learned in this video.